Problem
For different combinations of selection bits and input carry, we can perform different arithmetic operations as found in this book (Figure 1, given below). Similarly, for different ...
i am using an inline compiler (https://www.edaplayground.com/) and im not understanding the online compilers error message. I am trying to build the boolean expression (a * !b) + (b * !c) + (!b * c).
...
I'm just doing a project "design a dual-core processor based on RISC-V ISA no pipeline, no private or share cache and 2 cores are shared a data memory". I have designed RISC V single core processor ...
I recently had a project where I had to design a digital circuit. I got it working but my TA told me I need to avoid using constants. I used constants for comparisons at my gates and was wondering ...
Why does hamming code use the inequality sign?
I understand the equation 2^r ≥ m + r + 1 helps me obtain the minimum number of parity bits necessary (r) for an m-bit message, but is there a deeper ...
Consider the following example:
parameter BITWIDTH = 16;
This works:
logic [1:0][BITWIDTH-1:0] var = {16'h30, 16'h40};
This doesn't work:
logic [1:0][BITWIDTH-1:0] var = {BITWIDTH'h30, BITWIDTH'...
In this adder-subtractor design with the "M" input as the flag for subtraction, 0 minus 0 seems to provide the incorrect Cout. Let's assume that we're only using one full adder here (ignore A1/B1, A2/...
A sequential circuit consists of two D flip-flops; X, Y, two inputs A and B and one output Z. Clock pulse is active high. The next state and output equations of the circuit are as follows:
X(t+1) = (...
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is ? and also construct the circuit design.
My Approach:
...
I was reading a book for Digital Logic design using verilog coding and RTL synthesis. There was this sentence which is not clear to me - Latches are transparent to half of the clock cycle. Means?
I'm trying to implement a division algorithm in vhdl. To do that the first step is to double the amount of bits that are in the dividend and divisor. The next step is to perform a subtraction with ...
I need to implement a digital logic circuit with logic gates such as AND, OR, NOT, ADDER (and so on..), that gets an 8 bits binary number and return the number of the longest consecutive 1's in the ...
In Verilog/VHDL, lets say I have a 4 bit counter, and a flag that should be asserted when the counter equals between 4 and 8. There are two ways to implement this
if((cntr>=4)&&(cntr&...
im having a problem in my java exercice
the question is saying
The program will end when the sum of even is >= 50 or the sum of odd is >= 49.
so while solving it i tried to use
while (sumeven < ...
I have this circuit:
I need to:
find the output z
make it a canonical SOP
writing the minimal POS
finally expressing z with only NAND ports.
I'd like to receive suggestion(tricks?)/correction on ...